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- 安徽师范大学
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#include <hidef.h> /* common defines and macros */
#include "derivative.h" /* derivative-specific definitions */
typedef unsigned char uchar;
typedef unsigned int uint;
//IO¶Ë¿Ú¶¨Òå
#define CSN PORTE_PE2
#define MOSI PORTE_PE3
#define IRQ PORTE_PE4
#define MISO PORTE_PE5
#define SCK PORTE_PE6
#define CE PORTE_PE7
#define BUS_CLOCK 80000000 //×ÜÏßƵÂÊ
#define OSC_CLOCK 16000000 //¾§ÕñƵÂÊ
uchar TxBuf[32]=
{
0x01,0x02,0x03,0x4,0x05,0x06,0x07,0x08,
0x09,0x10,0x11,0x12,0x13,0x14,0x15,0x16,
0x17,0x18,0x19,0x20,0x21,0x22,0x23,0x24,
0x25,0x26,0x27,0x28,0x29,0x30,0x31,0x32,
};
#define TX_ADR_WIDTH 5 // 5 uints TX address width
#define RX_ADR_WIDTH 5 // 5 uints RX address width
#define TX_PLOAD_WIDTH 32 // 20 uints TX payload
#define RX_PLOAD_WIDTH 32 // 20 uints TX payload
uint const TX_ADDRESS[TX_ADR_WIDTH]= {0x34,0x43,0x10,0x10,0x01}; //±¾µØµØÖ·
uint const RX_ADDRESS[RX_ADR_WIDTH]= {0x34,0x43,0x10,0x10,0x01}; //½ÓÊÕµØÖ·
//NRF24L01¼Ä´æÆ÷Ö¸Áî
#define READ_REG 0x00 // ¶Á¼Ä´æÆ÷Ö¸Áî
#define WRITE_REG 0x20 // д¼Ä´æÆ÷Ö¸Áî
#define RD_RX_PLOAD 0x61 // ¶ÁÈ¡½ÓÊÕÊý¾ÝÖ¸Áî
#define WR_TX_PLOAD 0xA0 // д´ý·¢Êý¾ÝÖ¸Áî
#define FLUSH_TX 0xE1 // ³åÏ´·¢ËÍ FIFOÖ¸Áî
#define FLUSH_RX 0xE2 // ³åÏ´½ÓÊÕ FIFOÖ¸Áî
#define REUSE_TX_PL 0xE3 // ¶¨ÒåÖظ´×°ÔØÊý¾ÝÖ¸Áî
#define NOP 0xFF // ±£Áô
//SPI(nRF24L01)¼Ä´æÆ÷µØÖ·
#define CONFIG 0x00 // ÅäÖÃÊÕ·¢×´Ì¬£¬CRCУÑéģʽÒÔ¼°ÊÕ·¢×´Ì¬ÏìÓ¦·½Ê½
#define EN_AA 0x01 // ×Ô¶¯Ó¦´ð¹¦ÄÜÉèÖÃ
#define EN_RXADDR 0x02 // ¿ÉÓÃÐŵÀÉèÖÃ
#define SETUP_AW 0x03 // ÊÕ·¢µØÖ·¿í¶ÈÉèÖÃ
#define SETUP_RETR 0x04 // ×Ô¶¯ÖØ·¢¹¦ÄÜÉèÖÃ
#define RF_CH 0x05 // ¹¤×÷ƵÂÊÉèÖÃ
#define RF_SETUP 0x06 // ·¢ÉäËÙÂÊ¡¢¹¦ºÄ¹¦ÄÜÉèÖÃ
#define STATUS 0x07 // ״̬¼Ä´æÆ÷
#define OBSERVE_TX 0x08 // ·¢Ëͼà²â¹¦ÄÜ
#define CD 0x09 // µØÖ·¼ì²â
#define RX_ADDR_P0 0x0A // ƵµÀ0½ÓÊÕÊý¾ÝµØÖ·
#define RX_ADDR_P1 0x0B // ƵµÀ1½ÓÊÕÊý¾ÝµØÖ·
#define RX_ADDR_P2 0x0C // ƵµÀ2½ÓÊÕÊý¾ÝµØÖ·
#define RX_ADDR_P3 0x0D // ƵµÀ3½ÓÊÕÊý¾ÝµØÖ·
#define RX_ADDR_P4 0x0E // ƵµÀ4½ÓÊÕÊý¾ÝµØÖ·
#define RX_ADDR_P5 0x0F // ƵµÀ5½ÓÊÕÊý¾ÝµØÖ·
#define TX_ADDR 0x10 // ·¢Ë͵ØÖ·¼Ä´æÆ÷
#define RX_PW_P0 0x11 // ½ÓÊÕƵµÀ0½ÓÊÕÊý¾Ý³¤¶È
#define RX_PW_P1 0x12 // ½ÓÊÕƵµÀ0½ÓÊÕÊý¾Ý³¤¶È
#define RX_PW_P2 0x13 // ½ÓÊÕƵµÀ0½ÓÊÕÊý¾Ý³¤¶È
#define RX_PW_P3 0x14 // ½ÓÊÕƵµÀ0½ÓÊÕÊý¾Ý³¤¶È
#define RX_PW_P4 0x15 // ½ÓÊÕƵµÀ0½ÓÊÕÊý¾Ý³¤¶È
#define RX_PW_P5 0x16 // ½ÓÊÕƵµÀ0½ÓÊÕÊý¾Ý³¤¶È
#define FIFO_STATUS 0x17 // FIFOÕ»ÈëÕ»³ö״̬¼Ä´æÆ÷ÉèÖÃ
void Delay(unsigned int s);
void inerDelay_us(unsigned int n);
void init_NRF24L01(void);
uint SPI_RW(uint uchar);
uchar SPI_Read(uchar reg);
void SetRX_Mode(void);
uint SPI_RW_Reg(uchar reg, uchar value);
uint SPI_Read_Buf(uchar reg, uchar *pBuf, uchar uchars);
uint SPI_Write_Buf(uchar reg, uchar *pBuf, uchar uchars);
unsigned char nRF24L01_RxPacket(unsigned char* rx_buf);
void nRF24L01_TxPacket(unsigned char * tx_buf);
void INIT_PLL(void)
{
CLKSEL &= 0x7f; //ÉèÖÃOSCCLK×÷ΪϵͳʱÖÓ
PLLCTL &= 0x8F; //½ûÖ¹ËøÏà»·
//PLLCLK=2¡ÁOSCCLK¡Á(SYNR+1)/(REFDV+1), fbus=PLLCLK/2
#if(BUS_CLOCK == 120000000)
SYNR = 0xcd;
#elif(BUS_CLOCK == 104000000)
SYNR = 0xcc;
#elif(BUS_CLOCK == 96000000)
SYNR = 0xcb;
#elif(BUS_CLOCK == 88000000)
SYNR = 0xca;
#elif(BUS_CLOCK == 80000000)
SYNR = 0xc9;
#elif(BUS_CLOCK == 72000000)
SYNR = 0xc8;
#elif(BUS_CLOCK == 64000000)
SYNR = 0xc7;
#elif(BUS_CLOCK == 56000000)
SYNR = 0xc6;
#elif(BUS_CLOCK == 48000000)
SYNR = 0xc5;
#elif(BUS_CLOCK == 40000000)
SYNR = 0x44;
#elif(BUS_CLOCK == 32000000)
SYNR = 0x43;
#elif(BUS_CLOCK == 24000000)
SYNR = 0x42;
#elif(BUS_CLOCK == 16000000)
SYNR = 0x01;
#endif
REFDV = 0x81;
PLLCTL |=0x70; //ʹÄÜËøÏà»·
_asm(nop);
_asm(nop);
while(!(CRGFLG&0x08)); //PLLCLKËø¶¨
CLKSEL |= 0x80; //ÉèÖÃ LLCLKΪϵͳʱÖÓ
}
void Delay(unsigned int s)
{
unsigned int i;
for(i=0; i<s; i++);
for(i=0; i<s; i++);
}
uint sta = 0;
#define RX_DR sta&0x40 // RX_DR=sta^6;
#define TX_DS sta&0x20 // TX_DS=sta^5;
#define MAX_RT sta&0x10 // MAX_RT=sta^4;
void inerDelay_us(unsigned int n)
{
for(;n>0;n--)
{
_asm(nop);
_asm(nop);
_asm(nop);
_asm(nop);
}
}
void init_NRF24L01(void)
{
inerDelay_us(100); //Ð޸Ĺý
CE=0; // chip enable
CSN=1; // Spi disable
SCK=0; // Spi clock line init high
SPI_Write_Buf(WRITE_REG + TX_ADDR, TX_ADDRESS, TX_ADR_WIDTH); // д±¾µØµØÖ·
SPI_Write_Buf(WRITE_REG + RX_ADDR_P0, RX_ADDRESS, RX_ADR_WIDTH); // д½ÓÊն˵ØÖ·
SPI_RW_Reg(WRITE_REG + EN_AA, 0x01); // ƵµÀ0×Ô¶¯ ACKÓ¦´ðÔÊÐí
SPI_RW_Reg(WRITE_REG + EN_RXADDR, 0x01); // ÔÊÐí½ÓÊÕµØÖ·Ö»ÓÐƵµÀ0£¬Èç¹ûÐèÒª¶àƵµÀ¿ÉÒԲο¼Page21
SPI_RW_Reg(WRITE_REG + SETUP_RETR, 0x14); //ÖØ·¢µÈ´ý500us£¬ÖØ·¢4´Î
SPI_RW_Reg(WRITE_REG + RF_CH, 0X07); // ÉèÖÃÐŵÀ¹¤×÷Ϊ2.4GHZ£¬ÊÕ·¢±ØÐëÒ»ÖÂ
SPI_RW_Reg(WRITE_REG + RX_PW_P0, RX_PLOAD_WIDTH); //ÉèÖýÓÊÕÊý¾Ý³¤¶È£¬±¾´ÎÉèÖÃΪ32×Ö½Ú
SPI_RW_Reg(WRITE_REG + RF_SETUP, 0x07); //ÉèÖ÷¢ÉäËÙÂÊΪ1MHZ£¬·¢É书ÂÊΪ×î´óÖµ0dB
SPI_RW_Reg(WRITE_REG + CONFIG, 0x0e); // IRQÊÕ·¢Íê³ÉÖжÏÏìÓ¦£¬16λCRC£¬Ö÷·¢ËÍ
CE=1;
}
uint SPI_RW(uint ch)
{
uint bit_ctr = 0;
DDRE=0XCC;
for(bit_ctr = 0; bit_ctr < 8; bit_ctr++) // output 8-bit
{
MOSI = ((ch & 0x80) == 0x80); // output 'ch', MSB to MOSI
ch = (ch << 1); // shift next bit into MSB..
SCK = 1; // Set SCK high..
ch |= MISO; // capture current MISO bit
SCK = 0; // ..then set SCK low again
}
return (ch); // return read ch
}
uchar SPI_Read(uchar reg)
{
uchar reg_val;
CSN = 0; // CSN low, initialize SPI communication...
SPI_RW(reg); // Select register to read from..
reg_val = SPI_RW(0); // ..then read registervalue
CSN = 1; // CSN high, terminate SPI communication
return(reg_val); // return register value
}
uint SPI_RW_Reg(uchar reg, uchar value)
{
uint status;
CSN = 0; // CSN low, init SPI transaction
status = SPI_RW(reg); // select register
SPI_RW(value); // ..and write value to it..
CSN = 1; // CSN high again
return(status); // return nRF24L01 status uchar
}
uint SPI_Read_Buf(uchar reg, uchar *pBuf, uchar uchars)
{
uint status,uchar_ctr;
CSN = 0; // Set CSN low, init SPI tranaction
status = SPI_RW(reg); // Select register to write to and read status uchar
for(uchar_ctr=0;uchar_ctr<uchars;uchar_ctr++)
pBuf[uchar_ctr] = SPI_RW(0); //
CSN = 1;
return(status); // return nRF24L01 status uchar
}
uint SPI_Write_Buf(uchar reg, uchar *pBuf, uchar uchars)
{
uint status,uchar_ctr;
CSN = 0;
status = SPI_RW(reg);
for(uchar_ctr=0; uchar_ctr<uchars; uchar_ctr++)
SPI_RW(*pBuf++);
CSN = 1;
return(status);
}
void SetRX_Mode(void)
{
CE=0;
SPI_RW_Reg(WRITE_REG + CONFIG, 0x0f);
CE = 1;
inerDelay_us(130);
}
unsigned char nRF24L01_RxPacket(unsigned char* rx_buf)
{
unsigned char revale=0;
sta=SPI_Read(STATUS);
if(RX_DR)
{
CE = 0; //SPIʹÄÜ
SPI_Read_Buf(RD_RX_PLOAD,rx_buf,TX_PLOAD_WIDTH);// read receive payload from RX_FIFO buffer
revale =1;
}
SPI_RW_Reg(WRITE_REG+STATUS,sta);
return revale;
}
void nRF24L01_TxPacket(unsigned char * tx_buf)
{
CE=0; //StandBy Iģʽ
SPI_Write_Buf(WRITE_REG + RX_ADDR_P0, TX_ADDRESS, TX_ADR_WIDTH);
SPI_Write_Buf(WR_TX_PLOAD, tx_buf, TX_PLOAD_WIDTH);
SPI_RW_Reg(WRITE_REG + CONFIG, 0x0e);
CE=1;
inerDelay_us(15);
CE=0;
inerDelay_us(15);
}
/*void SetTxMode(void)
{
CE=0;
SPI_Write_Buf(WRITE_REG + TX_ADDR, TX_ADDRESS, TX_ADR_WIDTH);
SPI_Write_Buf(WRITE_REG + RX_ADDR_P0, RX_ADDRESS, RX_ADR_WIDTH);
// SPI_W_Reg(WRITE_REG + CONFIG, 0x0f);
SPI_RW_Reg(WRITE_REG + EN_AA, 0x00);
SPI_RW_Reg(WRITE_REG + EN_RXADDR, 0x00);
SPI_RW_Reg(WRITE_REG + SETUP_RETR, 0x00);
// SPI_W_Reg(WRITE_REG + SETUP_AW, 0x03); // Setup address width=5 bytes
// SPI_W_Reg(WRITE_REG + RF_CH, 0);
SPI_RW_Reg(WRITE_REG + RF_SETUP, 0x07);
SPI_RW_Reg(WRITE_REG + RX_PW_P0, RX_PLOAD_WIDTH);
SPI_RW_Reg(WRITE_REG + CONFIG, 0x0e);
CE=1; // chip enable
inerDelay_us(500);
} */
void main(void)
{
DisableInterrupts;
INIT_PLL();
DDRE_DDRE2=1;
DDRE_DDRE3=1;
DDRE_DDRE4=0;
DDRE_DDRE5=0;
DDRE_DDRE6=1;
DDRE_DDRE7=1;
// SetTxMode();
init_NRF24L01() ;
nRF24L01_TxPacket(TxBuf); // Transmit Tx buffer data
Delay(6000);
EnableInterrupts;
for(;;)
{
nRF24L01_TxPacket(TxBuf); // Transmit Tx buffer data
Delay(20000);
SPI_RW_Reg(WRITE_REG+STATUS,0XFF);
}
}
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发表于 2013-3-30 11:20:33
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发表于 2013-3-30 11:41:32