【MK60DN512VLQ10 】倍频问题

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【MK60DN512VLQ10 】倍频问题

要知道带Z的芯片似乎停产了？
而且带Z的芯片与不带Z的倍频操作是有区别的！！！
不知道你们发现没有！！！
以下倍频方案由官方提供的程序改来的，
但死活上不了160M，求大神解答～～～


这是运行结果：

1. int pll_init(int crystal_val,                   //外部时钟输入频率
   
2.              unsigned char hgo_val,             //For Low Power
   
3.              unsigned char erefs_val,           //选择内/外时钟
   
4.              signed char prdiv_val,             //分频系数
   
5.              signed char vdiv_val,              //倍频系数
   
6.              unsigned char mcgout_select)       // Use or not the output from this PLL as the MCGOUT
   
7. {
   
8.   unsigned char frdiv_val;
   
9.   unsigned char temp_reg;
   
10.   unsigned char prdiv, vdiv;
    
11.   short i;
    
12.   int ref_freq;
    
13.   int pll_freq;
    
14. 
    
15.   // check if in FEI mode
    
16.   if (!((((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) == 0x0) && // check CLKS mux has selcted FLL output
    
17.       (MCG_S & MCG_S_IREFST_MASK) &&                                  // check FLL ref is internal ref clk
    
18.       (!(MCG_S & MCG_S_PLLST_MASK))))                                 // check PLLS mux has selected FLL
    
19.   {
    
20.     return 0x1;                                                     // return error code
    
21.   }
    
22. 
    
23.   // check external frequency is less than the maximum frequency
    
24.   if  (crystal_val > 50000000) {return 0x21;}
    
25. 
    
26.   // check crystal frequency is within spec. if crystal osc is being used as PLL ref
    
27.   if (erefs_val)
    
28.   {
    
29.     if ((crystal_val < 3000000) || (crystal_val > 32000000)) {return 0x22;} // return 1 if one of the available crystal options is not available
    
30.   }
    
31. 
    
32.   // make sure HGO will never be greater than 1. Could return an error instead if desired.
    
33.   if (hgo_val > 0)
    
34.   {
    
35.     hgo_val = 1; // force hgo_val to 1 if > 0
    
36.   }
    
37. 
    
38.   // Check PLL divider settings are within spec.
    
39.   if ((prdiv_val < 1) || (prdiv_val > 25)) {return 0x41;}
    
40.   if ((vdiv_val < 24) || (vdiv_val > 55)) {return 0x42;}
    
41. 
    
42.   // Check PLL reference clock frequency is within spec(2M - 4M).
    
43.   ref_freq = crystal_val / prdiv_val;
    
44.   if ((ref_freq < 2000000) || (ref_freq > 4000000)) {return 0x43;}
    
45. 
    
46.   // Check PLL output frequency is within spec(现改为48M-250M).
    
47.   pll_freq = (crystal_val / prdiv_val) * vdiv_val;
    
48.   //if ((pll_freq < 48000000) || (pll_freq > 100000000)) {return 0x45;}
    
49.   if ((pll_freq < 48000000) || (pll_freq > 250000000)) {return 0x45;}
    
50. 
    
51.   // configure the MCG_C2 register
    
52.   // the RANGE value is determined by the external frequency. Since the RANGE parameter affects the FRDIV divide value
    
53.   // it still needs to be set correctly even if the oscillator is not being used
    
54.       
    
55.   temp_reg = MCG_C2;
    
56.   temp_reg &= ~(MCG_C2_RANGE0_MASK | MCG_C2_HGO0_MASK | MCG_C2_EREFS0_MASK); // clear fields before writing new values
    
57.    
    
58.   if (crystal_val <= 8000000) //高频 设置
    
59.   {
    
60.     temp_reg |= (MCG_C2_RANGE0(1) | (hgo_val << MCG_C2_HGO0_SHIFT) | (erefs_val << MCG_C2_EREFS0_SHIFT));
    
61.   }
    
62.   else                        //超高频 设置
    
63.   {
    
64.     temp_reg |= (MCG_C2_RANGE0(2) | (hgo_val << MCG_C2_HGO0_SHIFT) | (erefs_val << MCG_C2_EREFS0_SHIFT));
    
65.   }
    
66.   MCG_C2 = temp_reg;
    
67.   
    
68.   // determine FRDIV based on reference clock frequency
    
69.   // since the external frequency has already been checked only the maximum frequency for each FRDIV value needs to be compared here.
    
70.   if (crystal_val <= 1250000) {frdiv_val = 0;}
    
71.   else if (crystal_val <= 2500000) {frdiv_val = 1;}
    
72.   else if (crystal_val <= 5000000) {frdiv_val = 2;}
    
73.   else if (crystal_val <= 10000000) {frdiv_val = 3;}
    
74.   else if (crystal_val <= 20000000) {frdiv_val = 4;}
    
75.   else {frdiv_val = 5;}
    
76. 
    
77.   // Select external oscillator and Reference Divider and clear IREFS to start ext osc
    
78.   // If IRCLK is required it must be enabled outside of this driver, existing state will be maintained
    
79.   // CLKS=2, FRDIV=frdiv_val, IREFS=0, IRCLKEN=0, IREFSTEN=0
    
80.   temp_reg = MCG_C1;
    
81.   temp_reg &= ~(MCG_C1_CLKS_MASK | MCG_C1_FRDIV_MASK | MCG_C1_IREFS_MASK); // Clear values in these fields
    
82.   temp_reg |= (MCG_C1_CLKS(2) | MCG_C1_FRDIV(frdiv_val)); // Set the required CLKS and FRDIV values
    
83.   MCG_C1 = temp_reg;
    
84. 
    
85.   // if the external oscillator is used need to wait for OSCINIT to set
    
86.   if (erefs_val)
    
87.   {
    
88.     for (i = 0 ; i < 20000 ; i++)
    
89.     {
    
90.       if (MCG_S & MCG_S_OSCINIT0_MASK) break; // jump out early if OSCINIT sets before loop finishes
    
91.     }
    
92.   if (!(MCG_S & MCG_S_OSCINIT0_MASK)) return 0x23; // check bit is really set and return with error if not set
    
93.   }
    
94. 
    
95.   // wait for Reference clock Status bit to clear
    
96.   for (i = 0 ; i < 2000 ; i++)
    
97.   {
    
98.     if (!(MCG_S & MCG_S_IREFST_MASK)) break; // jump out early if IREFST clears before loop finishes
    
99.   }
    
100.   if (MCG_S & MCG_S_IREFST_MASK) return 0x11; // check bit is really clear and return with error if not set
     
101. 
     
102.   // Wait for clock status bits to show clock source is ext ref clk
     
103.   for (i = 0 ; i < 2000 ; i++)
     
104.   {
     
105.     if (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) == 0x2) break; // jump out early if CLKST shows EXT CLK slected before loop finishes
     
106.   }
     
107.   if (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2) return 0x1A; // check EXT CLK is really selected and return with error if not
     
108. 
     
109.   // Now in FBE
     
110.   // It is recommended that the clock monitor is enabled when using an external clock as the clock source/reference.
     
111.   // It is enabled here but can be removed if this is not required.
     
112.   MCG_C6 |= MCG_C6_CME0_MASK;
     
113.   
     
114.   // Configure PLL
     
115.   // Configure MCG_C5
     
116.   // If the PLL is to run in STOP mode then the PLLSTEN bit needs to be OR'ed in here or in user code.
     
117.   temp_reg = MCG_C5;
     
118.   temp_reg &= ~MCG_C5_PRDIV0_MASK;
     
119.   temp_reg |= MCG_C5_PRDIV0(prdiv_val - 1);    //set PLL ref divider
     
120.   MCG_C5 = temp_reg;
     
121. 
     
122.   // Configure MCG_C6
     
123.   // The PLLS bit is set to enable the PLL, MCGOUT still sourced from ext ref clk
     
124.   // The loss of lock interrupt can be enabled by seperately OR'ing in the LOLIE bit in MCG_C6
     
125.   temp_reg = MCG_C6; // store present C6 value
     
126.   temp_reg &= ~MCG_C6_VDIV0_MASK; // clear VDIV settings
     
127.   temp_reg |= MCG_C6_PLLS_MASK | MCG_C6_VDIV0(vdiv_val - 24); // write new VDIV and enable PLL
     
128.   MCG_C6 = temp_reg; // update MCG_C6
     
129. 
     
130.   // wait for PLLST status bit to set
     
131.   for (i = 0 ; i < 2000 ; i++)
     
132.   {
     
133.     if (MCG_S & MCG_S_PLLST_MASK) break; // jump out early if PLLST sets before loop finishes
     
134.   }
     
135.   if (!(MCG_S & MCG_S_PLLST_MASK)) return 0x16; // check bit is really set and return with error if not set
     
136. 
     
137.   // Wait for LOCK bit to set
     
138.   for (i = 0 ; i < 4000 ; i++)
     
139.   {
     
140.     if (MCG_S & MCG_S_LOCK0_MASK) break; // jump out early if LOCK sets before loop finishes
     
141.   }
     
142.   if (!(MCG_S & MCG_S_LOCK0_MASK)) return 0x44; // check bit is really set and return with error if not set
     
143. 
     
144.   // Use actual PLL settings to calculate PLL frequency
     
145.   prdiv = ((MCG_C5 & MCG_C5_PRDIV0_MASK) + 1);
     
146.   vdiv = ((MCG_C6 & MCG_C6_VDIV0_MASK) + 24);
     
147. 
     
148.   // now in PBE
     
149. 
     
150.   MCG_C1 &= ~MCG_C1_CLKS_MASK; // clear CLKS to switch CLKS mux to select PLL as MCG_OUT
     
151. 
     
152.   // Wait for clock status bits to update
     
153.   for (i = 0 ; i < 2000 ; i++)
     
154.   {
     
155.     if (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) == 0x3) break; // jump out early if CLKST = 3 before loop finishes
     
156.   }
     
157.   if (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x3) return 0x1B; // check CLKST is set correctly and return with error if not
     
158. 
     
159.   // Now in PEE
     
160.   
     
161.   return ((crystal_val / prdiv) * vdiv); //MCGOUT equals PLL output frequency
     
162. } // pll_init

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