/*==========================================================================
FTM1c0 PWM输出初始化函数
The edge-aligned mode is selected when (QUADEN = 0), (DECAPEN = 0), (COMBINE
= 0), (CPWMS = 0), and (MSnB = 1).
K60P144M100SF2RM.pdf P1011 39.4.6 Edge-Aligned PWM (EPWM) Mode
The EPWM period is determined by (MOD - CNTIN + 0x0001) and the pulse width
(duty cycle) is determined by (CnV - CNTIN).
//==========================================================================*/
void hw_FTM1_init(void)
{
//SIM_SOPT4|=SIM_SOPT4_FTM1FLT0_MASK;
/* Turn on all port clocks */
SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK;
/* Enable the function on PTA8 */
PORTA_PCR8 = PORT_PCR_MUX(0x3)| PORT_PCR_DSE_MASK;; // FTM is alt3 function for this pin
//FTM1_SC = FTM_SC_PS(0) | FTM_SC_CLKS(1);
//FTM1_SC=0X0F;
FTM1_SC = 0x28; //not enable the interrupt mask
//FTM1_SC=0X1F; //BIT5 0 FTM counter operates in up counting mode.
//1 FTM counter operates in up-down counting mode.
//BIT43 FTM1_SC|=FTM1_SC_CLKS_MASK;
//00 No clock selected (This in effect disables the FTM counter.)
//01 System clock
//10 Fixed frequency clock
//11 External clock
//BIT210 FTM1_SC|=FTM1_SC_PS_MASK;
//100M MOD=2000; MOD=4000; MOD=1000;
//000 Divide by 1---12KHZ 6K 24k
//001 Divide by 2--- 6KHZ
//010 Divide by 4--- 3K
//011 Divide by 8--- 1.5K
//100 Divide by 16---750
//101 Divide by 32---375
//110 Divide by 64---187.5HZ
//111 Divide by 128--93.75hz
FTM1_MODE |= FTM_MODE_WPDIS_MASK;
//BIT1 Initialize the Channels Output
//FTMEN is bit 0, need to set to zero so DECAPEN can be set to 0
FTM1_MODE &= ~1;
//BIT0 FTM Enable
//0 Only the TPM-compatible registers (first set of registers) can be used without any restriction. Do not use the FTM-specific registers.
//1 All registers including the FTM-specific registers (second set of registers) are available for use with no restrictions.
FTM1_OUTMASK=0XFE; //0 Channel output is not masked. It continues to operate normally.
//1 Channel output is masked. It is forced to its inactive state.
FTM1_COMBINE=0; //Function for Linked Channels (FTMx_COMBINE)
FTM1_OUTINIT=0;
FTM1_EXTTRIG=0; //FTM External Trigger (FTMx_EXTTRIG)
FTM1_POL=0; //Channels Polarity (FTMx_POL)
//0 The channel polarity is active high.
//1 The channel polarity is active low.
//Set Edge Aligned PWM
FTM1_QDCTRL &=~FTM_QDCTRL_QUADEN_MASK;
//QUADEN is Bit 1, Set Quadrature Decoder Mode (QUADEN) Enable to 0, (disabled)
//FTM0_SC = 0x16; //Center Aligned PWM Select = 0, sets FTM Counter to operate in up counting mode,
//it is field 5 of FTMx_SC (status control) - also setting the pre-scale bits here
FTM1_INVCTRL=0; //反转控制
FTM1_SWOCTRL=0; //软件输出控制F TM Software Output Control (FTMx_SWOCTRL)
FTM1_PWMLOAD=0; //FTM PWM Load
//BIT9: 0 Loading updated values is disabled.
//1 Loading updated values is enabled.
FTM1_CNTIN=0; //Counter Initial Value
FTM1_MOD=1000; //Modulo value,The EPWM period is determined by (MOD - CNTIN + 0x0001)
//采用龙丘时钟初始化函数，可以得到4分频的频率，系统60M频率时，PWM频率是15M,以此类推
//PMW频率=X系统频率/4/(2^FTM1_SC_PS)/FTM1_MOD
FTM1_C0V=500; //设置 the pulse width(duty cycle) is determined by (CnV - CNTIN).
FTM1_CNT=0; //只有低16位可用
}
//锁相环频率为50/12*54=225M测试函数
void pllinit225M(void)
{
uint32_t temp_reg;
//使能IO端口时钟
SIM_SCGC5 |= (SIM_SCGC5_PORTA_MASK
| SIM_SCGC5_PORTB_MASK
| SIM_SCGC5_PORTC_MASK
| SIM_SCGC5_PORTD_MASK
| SIM_SCGC5_PORTE_MASK );
//这里处在默认的FEI模式
//首先移动到FBE模式
MCG_C2 = 0;
//MCG_C2 = MCG_C2_RANGE(2) | MCG_C2_HGO_MASK | MCG_C2_EREFS_MASK;
//初始化晶振后释放锁定状态的振荡器和GPIO
SIM_SCGC4 |= SIM_SCGC4_LLWU_MASK;
LLWU_CS |= LLWU_CS_ACKISO_MASK;
//选择外部晶振，参考分频器，清IREFS来启动外部晶振
//011 If RANGE = 0, Divide Factor is 8; for all other RANGE values, Divide Factor is 256.
MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3);
//等待晶振稳定
//while (!(MCG_S & MCG_S_OSCINIT_MASK)){} //等待锁相环初始化结束
while (MCG_S & MCG_S_IREFST_MASK){} //等待时钟切换到外部参考时钟
while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2){}
//设置VCO分频器，使能PLL为100MHz, LOLIE=0, PLLS=1, CME=0, VDIV=26
MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(30); //VDIV = 31 (x54)
//VDIV = 26 (x50)
while (!(MCG_S & MCG_S_PLLST_MASK)){}; // wait for PLL status bit to set
while (!(MCG_S & MCG_S_LOCK_MASK)){}; // Wait for LOCK bit to set
//选择外部晶振，参考分频器，清IREFS来启动外部晶振
//011 If RANGE = 0, Divide Factor is 8; for all other RANGE values, Divide Factor is 256.
MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3);
//等待晶振稳定
//while (!(MCG_S & MCG_S_OSCINIT_MASK)){} //等待锁相环初始化结束
while (MCG_S & MCG_S_IREFST_MASK){} //等待时钟切换到外部参考时钟
while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2){}
//设置VCO分频器，使能PLL为100MHz, LOLIE=0, PLLS=1, CME=0, VDIV=26
MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(30); //VDIV = 31 (x54)
//VDIV = 26 (x50)
while (!(MCG_S & MCG_S_PLLST_MASK)){}; // wait for PLL status bit to set
while (!(MCG_S & MCG_S_LOCK_MASK)){}; // Wait for LOCK bit to set
//选择外部晶振，参考分频器，清IREFS来启动外部晶振
//011 If RANGE = 0, Divide Factor is 8; for all other RANGE values, Divide Factor is 256.
MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3);
//等待晶振稳定
//while (!(MCG_S & MCG_S_OSCINIT_MASK)){} //等待锁相环初始化结束
while (MCG_S & MCG_S_IREFST_MASK){} //等待时钟切换到外部参考时钟
while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2){}
//设置VCO分频器，使能PLL为100MHz, LOLIE=0, PLLS=1, CME=0, VDIV=26
MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(30); //VDIV = 31 (x54)
//VDIV = 26 (x50)
while (!(MCG_S & MCG_S_PLLST_MASK)){}; // wait for PLL status bit to set
while (!(MCG_S & MCG_S_LOCK_MASK)){}; // Wait for LOCK bit to set
//选择外部晶振，参考分频器，清IREFS来启动外部晶振
//011 If RANGE = 0, Divide Factor is 8; for all other RANGE values, Divide Factor is 256.
MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3);
//等待晶振稳定
//while (!(MCG_S & MCG_S_OSCINIT_MASK)){} //等待锁相环初始化结束
while (MCG_S & MCG_S_IREFST_MASK){} //等待时钟切换到外部参考时钟
while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2){}
//设置VCO分频器，使能PLL为100MHz, LOLIE=0, PLLS=1, CME=0, VDIV=26
MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(30); //VDIV = 31 (x54)
//VDIV = 26 (x50)
while (!(MCG_S & MCG_S_PLLST_MASK)){}; // wait for PLL status bit to set
while (!(MCG_S & MCG_S_LOCK_MASK)){}; // Wait for LOCK bit to set
//选择外部晶振，参考分频器，清IREFS来启动外部晶振
//011 If RANGE = 0, Divide Factor is 8; for all other RANGE values, Divide Factor is 256.
MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3);
//等待晶振稳定
//while (!(MCG_S & MCG_S_OSCINIT_MASK)){} //等待锁相环初始化结束
while (MCG_S & MCG_S_IREFST_MASK){} //等待时钟切换到外部参考时钟
while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2){}
//设置VCO分频器，使能PLL为100MHz, LOLIE=0, PLLS=1, CME=0, VDIV=26
MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(30); //VDIV = 31 (x54)
//VDIV = 26 (x50)
while (!(MCG_S & MCG_S_PLLST_MASK)){}; // wait for PLL status bit to set
while (!(MCG_S & MCG_S_LOCK_MASK)){}; // Wait for LOCK bit to set
//选择外部晶振，参考分频器，清IREFS来启动外部晶振
//011 If RANGE = 0, Divide Factor is 8; for all other RANGE values, Divide Factor is 256.
MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3);
//等待晶振稳定
//while (!(MCG_S & MCG_S_OSCINIT_MASK)){} //等待锁相环初始化结束
while (MCG_S & MCG_S_IREFST_MASK){} //等待时钟切换到外部参考时钟
while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2){}
//设置VCO分频器，使能PLL为100MHz, LOLIE=0, PLLS=1, CME=0, VDIV=26
MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(30); //VDIV = 31 (x54)
//VDIV = 26 (x50)
while (!(MCG_S & MCG_S_PLLST_MASK)){}; // wait for PLL status bit to set
while (!(MCG_S & MCG_S_LOCK_MASK)){}; // Wait for LOCK bit to set
//选择外部晶振，参考分频器，清IREFS来启动外部晶振
//011 If RANGE = 0, Divide Factor is 8; for all other RANGE values, Divide Factor is 256.
MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3);
//等待晶振稳定
//while (!(MCG_S & MCG_S_OSCINIT_MASK)){} //等待锁相环初始化结束
while (MCG_S & MCG_S_IREFST_MASK){} //等待时钟切换到外部参考时钟
while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2){}
//设置VCO分频器，使能PLL为100MHz, LOLIE=0, PLLS=1, CME=0, VDIV=26
MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(31); //VDIV = 31 (x55)
//VDIV = 26 (x50)
while (!(MCG_S & MCG_S_PLLST_MASK)){}; // wait for PLL status bit to set
while (!(MCG_S & MCG_S_LOCK_MASK)){}; // Wait for LOCK bit to set
//选择外部晶振，参考分频器，清IREFS来启动外部晶振
//011 If RANGE = 0, Divide Factor is 8; for all other RANGE values, Divide Factor is 256.
MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3);
//等待晶振稳定
//while (!(MCG_S & MCG_S_OSCINIT_MASK)){} //等待锁相环初始化结束
while (MCG_S & MCG_S_IREFST_MASK){} //等待时钟切换到外部参考时钟
while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2){}
//设置VCO分频器，使能PLL为100MHz, LOLIE=0, PLLS=1, CME=0, VDIV=26
MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(31); //VDIV = 31 (x55)
//VDIV = 26 (x50)
while (!(MCG_S & MCG_S_PLLST_MASK)){}; // wait for PLL status bit to set
while (!(MCG_S & MCG_S_LOCK_MASK)){}; // Wait for LOCK bit to set
//选择外部晶振，参考分频器，清IREFS来启动外部晶振
//011 If RANGE = 0, Divide Factor is 8; for all other RANGE values, Divide Factor is 256.
MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3);
//等待晶振稳定
//while (!(MCG_S & MCG_S_OSCINIT_MASK)){} //等待锁相环初始化结束
while (MCG_S & MCG_S_IREFST_MASK){} //等待时钟切换到外部参考时钟
while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2){}
//设置VCO分频器，使能PLL为100MHz, LOLIE=0, PLLS=1, CME=0, VDIV=26
MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(26); //VDIV = 31 (x55)
//VDIV = 26 (x50)
while (!(MCG_S & MCG_S_PLLST_MASK)){}; // wait for PLL status bit to set
while (!(MCG_S & MCG_S_LOCK_MASK)){}; // Wait for LOCK bit to set
//选择外部晶振，参考分频器，清IREFS来启动外部晶振
//011 If RANGE = 0, Divide Factor is 8; for all other RANGE values, Divide Factor is 256.
MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3);
//等待晶振稳定
//while (!(MCG_S & MCG_S_OSCINIT_MASK)){} //等待锁相环初始化结束
while (MCG_S & MCG_S_IREFST_MASK){} //等待时钟切换到外部参考时钟
while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2){}
//设置VCO分频器，使能PLL为100MHz, LOLIE=0, PLLS=1, CME=0, VDIV=26
MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(26); //VDIV = 31 (x55)
//VDIV = 26 (x50)
while (!(MCG_S & MCG_S_PLLST_MASK)){}; // wait for PLL status bit to set
while (!(MCG_S & MCG_S_LOCK_MASK)){}; // Wait for LOCK bit to set
//选择外部晶振，参考分频器，清IREFS来启动外部晶振
//011 If RANGE = 0, Divide Factor is 8; for all other RANGE values, Divide Factor is 256.
MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3);
//等待晶振稳定
//while (!(MCG_S & MCG_S_OSCINIT_MASK)){} //等待锁相环初始化结束
while (MCG_S & MCG_S_IREFST_MASK){} //等待时钟切换到外部参考时钟
while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2){}
//设置VCO分频器，使能PLL为100MHz, LOLIE=0, PLLS=1, CME=0, VDIV=26
MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(16); //VDIV = 31 (x55)
//VDIV = 26 (x50)
//VDIV = 16 (x40)
while (!(MCG_S & MCG_S_PLLST_MASK)){}; // wait for PLL status bit to set
while (!(MCG_S & MCG_S_LOCK_MASK)){}; // Wait for LOCK bit to set
//选择外部晶振，参考分频器，清IREFS来启动外部晶振
//011 If RANGE = 0, Divide Factor is 8; for all other RANGE values, Divide Factor is 256.
MCG_C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(3);
//等待晶振稳定
//while (!(MCG_S & MCG_S_OSCINIT_MASK)){} //等待锁相环初始化结束
while (MCG_S & MCG_S_IREFST_MASK){} //等待时钟切换到外部参考时钟
while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x2){}
//设置VCO分频器，使能PLL为100MHz, LOLIE=0, PLLS=1, CME=0, VDIV=26
MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(6); //VDIV = 31 (x55)
//VDIV = 26 (x50)
//VDIV = 6 (x30)
while (!(MCG_S & MCG_S_PLLST_MASK)){}; // wait for PLL status bit to set
while (!(MCG_S & MCG_S_LOCK_MASK)){}; // Wait for LOCK bit to set
