>请教一下关于S12DG128 ATD的一些相关问题</P><P>1、关于控制寄存器ATD0CTL3中FIFO的使用<BR> 假定要转换的序列为3，即通道3、4、5，转换模式为连续转换（SCAN=1）<BR> （1）当FIFO=0时，转换结果是存储在ATD0DR0-ATD0DR2中，还是存储在ATD0DR3-ATD0DR5中？<BR>当一个序列转换结束后，下一个转换序列的结果还是存储在这几个对应寄存器中，对吗？<BR> （2）当FIFO=1时，转换结果是存储在ATD0DR0-ATD0DR2中，还是存储在ATD0DR3-ATD0DR5中？<BR>当一个序列转换结束后，下一个转换序列的结果是存储在紧接其后的几个对应寄存器中，循环存储（即存储到ATD0DR7后，<BR>返回ATD0DR0，在从ATD0DR0-ATD0DR7存储），对吗？</P><P>2、在HC12系列单片机中，当控制寄存器5中S8CM=0（即一个转换序列转4次），MULT=0(即单通道转换)时，<BR>是在一个转换序列中对一个通道连续转换四次；而在S12系列中，当转换序列长度设置为1，MULT=0时，<BR>每进行一个序列的转换是对该通道转换一次，还是转换四次？</P>>看看英文文档的说明：</P><P><FONT size=5>If this bit is zero (non-FIFO mode), the A/D conversion results map into the result registers based on the conversion sequence; <FONT color=#f70938>the result of the first conversion appears in the first result register, the second result in the second result register, and so on.</FONT></FONT></P><P><FONT color=#f70938 size=5>Please Notice here : "the result of the first conversion appears in the first result register, </FONT><FONT color=#f70938 size=5>the second result in the second result register, and so on."</FONT></P>><FONT size=4>FIFO — Result Register FIFO Mode<BR>If this bit is zero (non-FIFO mode), the A/D conversion results map into the result registers based on<BR>the conversion sequence; the result of the first conversion appears in the first result register, the second result in the second result register, and so on.<BR>If this bit is one (FIFO mode) the conversion counter is not reset at the beginning or ending of a<BR>conversion sequence; sequential conversion results are placed in consecutive result registers. In a<BR>continuously scanning conversion sequence, the result register counter will wrap around when it<BR>reaches the end of the result register file. The conversion counter value (CC2-0 in ATDSTAT0) can<BR>be used to determine where in the result register file, the current conversion result will be placed.<BR>Aborting a conversion or starting a new conversion by write to an ATDCTL register (ATDCTL5-0)<BR>clears the conversion counter even if FIFO=1. So the first result of a new conversion sequence, started by writing to ATDCTL5, will always be place in the first result register (ATDDDR0). Intended usage of FIFO mode is continuos conversion (SCAN=1) or triggered conversion (ETRIG=1).<BR>Which result registers hold valid data can be tracked using the conversion complete flags. Fast flag<BR>clear mode may or may not be useful in a particular application to track valid data.<BR>1 = Conversion results are placed in consecutive result registers (wrap around at end).<BR>0 = Conversion results are placed in the corresponding result register up to the selected sequence<BR>length.</FONT></P>| 欢迎光临 智能车制作 (http://111.231.132.190/) | Powered by Discuz! X3.2 |