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标题: K60FX512VLQ15的时钟频率配置问题 [打印本页]

作者: 小蚩尤 时间: 2017-2-19 13:52
标题: K60FX512VLQ15的时钟频率配置问题
#elif (CLOCK_SETUP == 3)
  /* SIM_SCGC5: PORTA=1 */
  SIM->SCGC5 |= (uint32_t)0x0200UL;    /* Enable clock gate for ports to enable pin routing *///选取时钟端口PORTA
  /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=3,OUTDIV4=5,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
  SIM->CLKDIV1 = (uint32_t)0x01350000UL; /* Update system prescalers *///Core clocks1分频 Bus clocks2分频
  /* SIM_SOPT2: PLLFLLSEL=1 */
  SIM->SOPT2 = (uint32_t)((SIM->SOPT2 & (uint32_t)~0x00020000UL) | (uint32_t)0x00010000UL); /* Select PLL 0 as a clock source for various peripherals *///选择PLL0作为外设时钟源
  /* SIM_SOPT1: OSC32KSEL=0 */
  SIM->SOPT1 &= (uint32_t)~0x00080000UL; /* System oscillator drives 32 kHz clock for various peripherals *///各种外设的系统震荡器时钟源为32K
  /* SIM_SCGC1: OSC1=1 */
  SIM->SCGC1 |= (uint32_t)0x20UL;//选择OSC1时钟源
  /* PORTA_PCR18: ISF=0,MUX=0 */
  PORTA->PCR[18] &= (uint32_t)~0x01000700UL;
  /* Switch to FBE Mode */
  /* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
  OSC0->CR = (uint8_t)0x80U; //启用外部参考时钟OSC0
  /* OSC1_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
  OSC1->CR = (uint8_t)0x80U; //启用外部参考时钟OSC1
  /* MCG_C7: OSCSEL=0 */
  MCG->C7 &= (uint8_t)~(uint8_t)0x01U;  //选择MCG中PLL的参考时钟为OSCCLOCK
  /* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
  MCG->C2 = (uint8_t)0x20U; //oscillator选择非常高的频率范围
  /* MCG_C1: CLKS=2,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
  MCG->C1 = (uint8_t)0xAAU; //选择MCGOUTCLK为外部参考时钟；进入FLL前的分频数为    ；选择FLL的时钟源为外部时钟源；MCGIRCLK允许使用内部参考时钟（不用了解）；
  /* MCG_C4: DMX32=0,DRST_DRS=0 */
  MCG->C4 &= (uint8_t)~(uint8_t)0xE0U;
  /* MCG_C5: PLLREFSEL0=0,PLLCLKEN0=0,PLLSTEN0=0,??=0,??=0,PRDIV0=4 */
  MCG->C5 = (uint8_t)0x04U; //选择OSC0为PLL0的外部参考时钟源；PRDIV0为5分频
  /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=24 */
  MCG->C6 = (uint8_t)0x18U; //  PLL0中VDIV0的倍频系数为40
  /* MCG_C11: PLLREFSEL1=0,PLLCLKEN1=0,PLLSTEN1=0,PLLCS=0,??=0,PRDIV1=0 */
  MCG->C11 = (uint8_t)0x00U;
  /* MCG_C12: LOLIE1=0,??=0,CME2=0,VDIV1=0 */
  MCG->C12 = (uint8_t)0x00U;
  while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
  }
  while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
  }
  /* Switch to PBE Mode */
  /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=24 */
  MCG->C6 = (uint8_t)0x58U;  //  PLL0中VDIV0的倍频系数为40
  while((MCG->S & 0x0CU) != 0x08U) { /* Wait until external reference clock is selected as MCG output */
  }
  while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until PLL locked *///等待PLL0解锁
  }
  /* Switch to PEE Mode */
  /* MCG->C1: CLKS=0,FRDIV=5,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
  MCG->C1 = (uint8_t)0x2AU;
  while((MCG->S & 0x0CU) != 0x0CU) { /* Wait until output of the PLL is selected */
  }
我用的是超核的库以上是我自己加的一项，不知道哪儿问题  就是不行！我把MCG->C6 = (uint8_t)0x58U（这样倍频40倍  出来应该是200M）;  改成MCG->C6 = (uint8_t)0x54U;也就是180M时就可以  其他都没变

作者: 小蚩尤 时间: 2017-2-19 13:53
求大神解救啊！我已经哭了，差了20M，心有不甘啊

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